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Allegrex Execution Model for Recompiler Authors

Posted
Updated
ByJstar269

Type: REFERENCE   Status: MAINTAINED   Scope: PSP Allegrex execution as observed by a static recompiler

This page is the CPU foundation for the rest of the knowledge base. “MIPS32-like” is useful orientation, but it is not a sufficient implementation contract: Allegrex combines a MIPS-derived integer core with PSP-specific instructions, a distinct coprocessor arrangement, delay-slot control flow, a PSP ABI, and a host-language translation boundary.

How We Know

guest instruction
      |
      v
decode -> architectural state update -> delay-slot effects
      |                                |
      v                                v
generated C ----------------------> HLE / dispatch boundary
      |
      v
host runtime preserves guest-visible state, not host ABI assumptions
Source-owned conceptual execution-state diagram.

Architectural state that matters

PRIOR ART: Allegrex exposes 32-bit general-purpose registers, HI/LO multiply-divide state, COP0 system control, COP1 scalar floating point, and COP2/VFPU. The public architecture page describes a MIPS32 4K/R4000-family relationship while also documenting PSP-specific instructions and omissions.

IMPLEMENTATION FACT: the current Nakagawa CpuState keeps GPRs, hi/lo, scalar FPU state, the 128-entry VFPU file, VFPU control, guest PC bookkeeping, and delay-slot state together. The runtime has no separate architectural link-register field: $ra is GPR 31.

  • Keep guest values explicitly 32-bit. Host long, pointer width, and implicit integer promotion are not PSP ABI definitions.
  • Preserve signed and unsigned interpretations at the operation boundary. A bit pattern can be a pointer, an unsigned address, a signed result, or a float without changing its stored 32 bits.
  • Use wider checked intermediates for multiply, address extent, and size arithmetic; narrow only at the architectural writeback point.

Control flow and delay slots

PRIOR ART: MIPS branches and jumps have an architectural delay slot. Branch-likely forms add annul behavior: a not-taken likely branch does not execute its slot. Calls and returns still expose the slot to the guest program.

IMPLEMENTATION FACT: code generation tracks delay-slot state explicitly, emits branch-slot effects in the correct order, and handles a slot that is also a branch target without executing it twice. A translated host call is therefore not a license to skip the guest slot or to update PC early.

  • Make the next-PC/slot relationship explicit in an interpreter or generated state machine.
  • Test taken, not-taken, likely-annulled, indirect, and link-producing forms separately.
  • Retain guest PC provenance at HLE, scheduler, and fault boundaries; a host return address is not a guest EPC.

Alignment, arithmetic, and faults

Aligned loads/stores and the MIPS left/right instructions are different contracts. Host x86 tolerance for unaligned access must not hide a guest alignment rule. Multi-byte operations crossing a guest-region boundary need whole-span validation before host access.

A title-oriented runtime normally implements a bounded fault policy rather than a complete Allegrex MMU/TLB. That policy must be explicit: which user-mode addresses map, which aliases are accepted, which invalid spans return an error, and which faults remain unsupported. Do not convert host memory permissiveness into PSP privilege.

COP1, COP2, and PSP-specific instructions

Keep COP1 scalar floating point separate from the VFPU: control/condition state, NaNs, infinities, signed zero, conversions, and rounding can diverge from host libm. COP2/VFPU uses a physical register file with scalar/vector/matrix views, prefixes, masks, and aliases; see VFPU Architecture for Binary Translation, VFPU Register Addressing, and VFPU Transcendentals.

The public Allegrex material also lists PSP-specific bit operations and control instructions such as halt, mfic, and mtic. Treat unsupported or privileged forms as visible gaps, not as generic MIPS no-ops.

ABI and host-language hazards

The PSP calling convention passes arguments through the documented register set and stack, preserves callee-saved registers, and returns values in $v0/$v1 as applicable. Generated C should bridge through an explicit guest state, not silently call host functions with a host ABI that happens to have the same number of arguments.

  • Do not left-shift negative signed values or rely on signed overflow.
  • Do not perform guest-pointer arithmetic before validating the guest span.
  • Do not use strict-aliasing-violating type punning for bit-preserving float/integer views.
  • Test optimization levels; undefined host behavior often appears only after optimization.

Do Not Infer

  • Allegrex is not interchangeable with an arbitrary MIPS32 implementation.
  • One generated-C route is not proof of full instruction or exception coverage.
  • Host OS threads, host exceptions, and host return addresses are not PSP scheduler, fault, or ABI semantics.
  • PPSSPP agreement is a differential signal, not independent hardware proof.

Related pages and open questions

Continue to VFPU Architecture, PSP Memory Model, Static Recompilation Architecture, and Open Research Questions. Remaining boundaries include precise exception entry, model/firmware differences, and instruction forms not exercised by current source-owned fixtures.

Primary sources

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