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Conflict: PSP Cache Capacity and Line-Size Wording

Posted
Updated
ByJstar269

Conflict ID: CONFLICT-CACHE-CAPACITY-001 · Status: OPEN / PRIOR-ART AMBIGUITY

Question

Is the Allegrex cache description 16 KiB instruction + 16 KiB data, or an unqualified 32 KiB L1 with 64-byte lines?

Claims in conflict

  • A: the current PSP Developer Wiki Allegrex wording describes 16 KiB I-cache plus 16 KiB D-cache.
  • B: an older dedicated Cache page describes a 32 KiB L1 and 64-byte lines.

Why they appear incompatible

The statements may describe a combined split cache, different documentation eras, model revisions, or one inaccurate summary. No source in the current corpus resolves that distinction.

Current status

OPEN. Do not publish an unqualified capacity or line-size claim. The evidence cells in the model matrix remain NOT TESTED.

Next discriminating experiment

EXP-CACHE-DMA-SMC-001 — controlled I-cache/D-cache working-set, alias, writeback, invalidate, and self-modifying-code tests with cross-model replication. The safe fixture uses owned RAM/code pages and no arbitrary MMIO.

Smallest supported conclusion

Both public wording variants exist; cache capacity/line-size applicability is unresolved until the scope and model are pinned.

Related: PSP Cache reference · planned experiment registry · Last reviewed: 2026-08-11.

Current source anchor — Wave 4

The current public implementation context was refreshed against docs/HARDWARE_ORACLE.md at main 04daf156; wording differences remain a provenance/documentation conflict, not a new cache measurement.

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